A Dynamic Random Access Memory ("DRAM"), as is known, contains a memory cell array having a plurality of memory cells Each memory cell is coupled to one of a plurality of word lines and one of a plurality of bit lines, arranged in matrix. Peripheral circuits control read and write operations of data into and out from the selected memory cell.
Each memory cell in the DRAM typically comprises a single MOSFET (metal-oxide-semiconductor field effect transistor) and a single capacitor. Data written into a memory cell is stored in the single capacitor of the memory cell. Thus, the logic state of the data is determined by the amount of the charge stored in the single capacitor. However, with such a structure the data stored in the single capacitor degrades over time due to current leakage. A refresh function is therefore provided to restore the original stored charge data level in the memory cell capacitor.
In known DRAMs, the refresh operation is automatically and repeatedly performed during a predetermined period. This operation is called a self-refresh operation, during which addresses for memory cells are sequentially generated in the . DRAM without using the externally generated addresses used to address memory cells during normal operation.
One conventional self-refresh used in a DRAM is described in Japanese Patent Publication No. 61 57079 (issued in 1986), entitled "A Dynamic Semiconductor Memory Device". In the '079 publication a self-refresh operation mode is enabled after a column address strobe ("CAS") occurs, a row address strobe occurs ("RAS"), and a predetermined time elapses. Known as CAS before RAS refresh mode (referred to as "CBR mode" hereinafter) as described it requires an active "low" state CAS signal followed by and active "low" state RAS signal at the appropriate time. To complete the initiation of the CBR mode, the row address strobe signal RAS must retain its activation level of "low" for a predetermined time lapse of, for example, 16 micro-seconds.
FIG. 1 shows the functional components of a DRAM employing the above described conventional self-refresh scheme and FIG. 2, illustrates the operation timing of the FIG. 1 DRAM the self refresh operation will be further described. A refresh control circuit 22 generates a refresh clock .PHI.RFSH. A CBR mode informing signal, generated by a control signal generator 20 which receives a row address strobe signal RAS, a column address strobe signal CAS and a write signal WEactivates the refresh control circuit 22. A refresh address counter 24 generates a plurality of internal refresh addresses each address having a plurality of internal refresh address signals Q.sub.0 -Q.sub.n-1 corresponding to each address bit position in response to the refresh clock .PHI.RFSH.
Referring to FIG. 2, which illustrates the refresh clock .PHI.RFSH and the internal refresh address signals Q.sub.0 -Q.sub.n-1, the refresh clock .PHI.RFSH is generated from the refresh control circuit 22 by an oscillator in response to receipt of the CBR mode informing signal. Once the refresh clock .PHI.RFSH is applied to the refresh address counter 24, a plurality of internal refresh address signals Q.sub.0 -Q.sub.n-1 are generated from the refresh address counter 24 and applied to a row decoder 12 for the purpose of selecting rows of memory cells in memory cell array 10 in a regular sequence. Each refresh address, composed of internal refresh address signals Q.sub.0 -Q.sub.n-1, is used to address one row of memory cells during a portion of the self-refresh operation.
However, it is impossible for the conventional self-refresh circuit, as shown in FIG. 1, to detect whether all the internal refresh addresses necessary to accomplish the self-refresh operation have been completely generated. It is also impossible to verify the internal self refresh cycle time as a substantial value. This therefore detracts from the reliability of the resulting DRAM.